MB84VD23381FJ Datasheet, PDF (48/54 Pages) Fujitsu Component Limited. – Stacked MCP (Multi-Chip Package) FLASH MEMORY & FCRAM

MB84VD23381FJ-80
• Standby Entry Timing after Read or Write (FCRAM)
CE1r
OE
tCHOX
tCHWX
WE
Active (Read)
Standby
Active (Write)
Standby
Note : Both tCHOX and tCHWX define the earliest entry timing for Standby mode. If either of timing is not satisfied, it
takes tRC (Min) period from either last address transition of A0 and A1, or CE1r Low to High transition.
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