MB86604L Datasheet, PDF (5/56 Pages) Fujitsu Component Limited. – SCSI-II Protocol Controller (with single-ended driver/receiver)

MB86604L
Phase name
Data-out phase
Data-in phase
Command phase
Status phase
Message-out phase
Message-in phase
MSG C/D
I/O
H
H
H
H
H
L
H
L
H
H
L
L
L
L
H
L
L
L
Transfer direction
Initiator
Target
→
←
→
←
→
←
Note: The SCSI interface input/output pins can be connected to a single-end type SCSI bus.
2. MPU Interface
Pin
number
Symbol*
Pin name
77
CS0
Chip select 0
80
CS1
Chip select 1
98, 97, 96, D15
95, 94, 93, to
92, 91
D8
99
UDP
89, 88, 87, D7
86, 85, 84, to
83, 82
D0
81
LDP
76, 75, 74, A4
73, 72
to
A0
2
RD
(R/W)
Data 15
to
data 8
Upper data
parity
Data 7
to
data 0
Lower data
parity
Address 4
to
address 0
Read
(read/write)
1
WR
Write
(LDS)
(lower data
strobe)
I/O
Function
I This is a chip select 0 pin used by MPU to select the SPC as an
I/O device. This is an active-low pin.
I This is a chip select 1 pin to select when MPU inputs/outputs the
data on DMA bus through SPC. This is an active-low pin.
I/O These pins are for the upper byte and parity bit of MPU data bus.
When the CS0 input is valid, these pins serve as I/O ports for the
SPC internal registers. When the CS1 input is valid, these pins
serve as I/O ports for the DMA bus data.
I/O These pins are for the lower byte and parity bit of the MPU data
bus. When the CS0 input is valid, these pins serve as I/O ports
for the SPC internal registers. When the CS1 input is valid, these
pins serve as I/O ports for the DMA bus data.
I These are address input pins to select the SPC internal
registers.
I In the 80-series mode, this is a read signal input pin (IORD or
RD) that MPU reads the SPC. This read signal pin is an active-
low. In the 68-series mode, this pin functions as the control
signal input (R/W) to control the read/write operation to the SPC.
In the read operation, this pin is an active-high. In the write
operation, this pin is an active-low.
I In the 80-series mode, this pin is a write signal input pin (IOWR
or WR) that MPU writes to the SPC. This write signal input pin is
active-low. In the 68-series mode, this pin function as the lower
data strobe signal input (LDS) that MPU outputs when the lower
byte of data bus is valid. The LDS pin is an active-low.
(Continued)
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