MB86604L Datasheet, PDF (20/56 Pages) Fujitsu Component Limited. – SCSI-II Protocol Controller (with single-ended driver/receiver)

MB86604L
• Register read timing
Parameter
Symbol
Base signal
Position*
Address (A4 to A0) set up time
Address (A4 to A0) hold time
CS0 set up time
CS0 hold time
R/W set up time
R/W hold time
UDS/LDS “L” level pulse time
Data output confirmation time
Data output disable time
INT signal ^{for INT non-hold mode}
clear time _{for INT hold mode}
UDS/LDS “L” tsuA
A
UDS/LDS “H” thA
B
UDS/LDS “L” tsuCS0
C
UDS/LDS “H” thCS0
D
UDS/LDS “L” tsuRW
E
UDS/LDS “H” thRW
F
—
twDS
G
UDS/LDS “L”
tvD
H
UDS/LDS “H” tDZ
I
UDS/LDS “L” tDH
J
UDS/LDS “H” tDH2
K
* : The position number indicates the position in the waveform.
Value
Unit
Min.
Max.
40
—
ns
20
—
ns
20
—
ns
10
—
ns
20
—
ns
20
—
ns
70
—
ns
—
70
ns
10
—
ns
—
50
ns
—
n tCLK + 50 ns
A4 to A0
CS0
R/W
UDS/LDS
D15 to D8, UDP
D7 to D0, LDP
A
t suA
C
t suCS0
B
t hA
D
t hCS0
E
t suRW
G
t wDS
F
t hRW
H
t vD
J
t DH
I
t DZ
Valid data
INT
K
t
*
DH2
INT
*: t DH2 is determined by a rising edge of the strobe signal which reads the step code for the last interrupt source.
Also, “n” indicates the division ratio.
20