MB86604L Datasheet, PDF (23/56 Pages) Fujitsu Component Limited. – SCSI-II Protocol Controller (with single-ended driver/receiver)

MB86604L
(5) DMA interface
The DMA access timing described in this section is not applicable in the following cases.
During SCSI input, when the data buffer is EMPTY or when one byte is stored
During SCSI output, when the data buffer is FULL or when 31 bytes are stored
When a parity error is detected (target)
When an error which pauses the transfer occurs at the SCSI interface
• 80 series handshake mode
(a) Write timing
Parameter
Symbol
Base signal
Position*
Value
Min.
Max.
Unit
DACK “L” assert time
DREQ “L” negate time
DREQ “H” assert time (8 bit)
DREQ “H” assert time (16 bit)
IOWR “L” assert time
DMBHE, DMA0 set up time
DMBHE, DMA0 hold time
IOWR “L” level pulse width
DACK “H” negate time
Input data set up time
Input data hold time
DREQ “H”
tRQAK
A
0
—
ns
DACK “L”
tAKRQ
B
—
40
ns
DACK “H”
tAKRQ1
C
—
50
ns
DACK “H”
tAKRQ2
C
—
2 tCLK + 40 ns
DACK “L”
tAKWR
D
0
—
ns
IOWR “L”
tsuDA
E
20
—
ns
IOWR “H”
thDA
F
20
—
ns
—
twWRL
G
40
—
ns
IOWR “L”
tWRAK1
H
1 tCLK
—
ns
IOWR “H”
tWRAK2
I
0
—
ns
IOWR “H”
tsuDMD
J
30
—
ns
IOWR “H”
thDMD
K
5
—
ns
* : The position number indicates the position in the waveform.
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