MB86604L Datasheet, PDF (16/56 Pages) Fujitsu Component Limited. – SCSI-II Protocol Controller (with single-ended driver/receiver)

MB86604L
• Register read timing
Parameter
Symbol
Base signal
Position*
Address (A4 to A0), BHE set up time
RD “L”
tsuA
A
Address (A4 to A0), Hold time
RD “H”
thA
B
CS0 set up time
RD “L”
tsuCS0
C
CS0 hold time
RD “H”
thCS0
D
RD “L” level pulse width
—
twRDL
E
Data output defined time
RD “L”
tvD
F
Data output disable time
RD “H”
tDZ
G
INT signal ^{for INT non-hold mode}
clear time _{for INT hold mode}
RD “L”
tDL
H
RD “H”
tDL2
I
* : The position number indicates the position in the waveform.
Value
Unit
Min.
Max.
40
—
ns
20
—
ns
20
—
ns
10
—
ns
70
—
ns
—
70
ns
10
—
ns
—
50
ns
—
n tCLK + 50 ns
A4 to A0
BHE
A
B
t suA
t hA
CS0
RD
D15 to D8, UDP
D7 to D0, LDP
C
t suCS0
E
t wRDL
D
t hCS0
F
t vD
H
t DL
G
t DZ
Valid data
INT
t DL2*
I
INT
*: t DL2 is determined by a rising edge of the strobe signal which reads the step code for the last interrupt source.
Also, “n” indicates the division ratio.
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