MB86604L Datasheet, PDF (34/56 Pages) Fujitsu Component Limited. – SCSI-II Protocol Controller (with single-ended driver/receiver)

MB86604L
(b) Output timing (initiator → target)
Parameter
Symbol
Base signal
Position*¹
Value
Min.
Max.
REQ “H” negate time
ACK “H” negate time
ACK “L”
tAKRQH
A
REQ “H”
tRQAKH
B
0
—
—
60
REQ “L” assert time
Time from output data valid to ACK “L” assert
*²
ACK “H”
—
tAKRQL
tDBAK
C
10
—
D
S • tCLK – 10 —
Output data hold time
REQ “H”
thDB
E
2 tCLK
—
ACK “L” assert time
REQ “L”
tRQAK1
F
—
40
*1: The position number indicates the position in the waveform.
*2: “S” value is based on the asychronous set up time setting register (address 17h).
Note: The output timing definitions are not applied when the data register is EMPTY in the data phase.
Unit
ns
ns
ns
ns
ns
ns
&'^REQ
ACK
DB7 to DB0
DBP
A
t AKRQH
B
t RQAKH
D
t DBAK
Valid data
E
t hDB
t RQAK2 ^*
C
t AKRQL
F
t RQAK1
D
t DBAK
Valid data
*: The REQ “H” → ACK “L” time (tRQAK2) is defined by either longer of (tRQAKH + tAKRQL + tRQAK1) or (thDB +
tDBAK) (see the output timing waveform).
34