MB86604L Datasheet, PDF (27/56 Pages) Fujitsu Component Limited. – SCSI-II Protocol Controller (with single-ended driver/receiver)

MB86604L
(b) Read timing
Parameter
Base signal
Symbol
Position*
DACK “L” assert time
DREQ “H”
tRQAK
A
DREQ “L” negate time
DREQ “H” assert time (8 bit)
DACK “L”
DACK “H”
tAKRQ
B
tAKRQ1
C
DREQ “H” assert time (16 bit)
DACK “H”
tAKRQ2
C
DMUDS/DMLDS “L” assert time
DMR/W set up time
DACK “L”
tAKDS
D
DMUDS/DMLDS “L” tsuRW
E
DMR/W hold time
DMUDS/DMLDS “H” thRW
F
DMUDS/DMLDS “L” level pulse width
—
twDSL
G
DACK “H” negate time
DMUDS/DMLDS “L” tDSAK1
H
DMUDS/DMLDS “H” tDSAK2
I
Data output defined time
Data output hold time
DMUDS/DMLDS “L” tvDMD
J
DMUDS/DMLDS “H” thDMD
K
* : The position number indicates the position in the waveform.
Value
Unit
Min.
Max.
0
—
ns
—
40
ns
—
50
ns
—
2 tCLK + 40 ns
0
—
ns
20
—
ns
20
—
ns
40
—
ns
1 tCLK
—
ns
0
—
ns
—
40
ns
10
—
ns
DREQ
A
t RQAK
B
t AKRQ
DACK
DMR/W
D
t AKDS
E
t suRW
DMUDS/DMLDS
DMD15 to DMD0
UDMDP, LDMDP
J
t vDMD
C
t AKRQ1/2
H
t DSAK1
I
t DSAK2
G
t wDSL
F
t hRW
K
t hDMD
Valid data
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