MB86604L Datasheet, PDF (14/56 Pages) Fujitsu Component Limited. – SCSI-II Protocol Controller (with single-ended driver/receiver)

MB86604L
4. AC Characteristics
(1) System clock
Parameter
Clock cycle time (CLK)
Clock “H” pulse width
Clock “L” pulse width
Clock rise time
Clock fall time
Symbol
tCLK
twCKH
twCKL
tCR
tCF
Position*
A
B
C
D
E
Value
Min.
Max.
25.0
50.0
10.0
—
10.0
—
—
10.0
—
10.0
Unit
ns
ns
ns
ns
ns
* : The position number indicates the position in the waveform.
Note: In case that the internal clock frequency and the input clock frequency are the same (i.e. when using the
divided-by-one mode), the clock pulse width (for “H” and “L”) must have at least 20 ns or longer.
CLK
3.5 V
1.5 V
B
t wCKH
E
t CF
A
t CLK
D
t CR
C
t wCKL
(2) System reset
Parameter
RESET “L” level pulse width
Symbol
twRSL
Value
Min.
Max.
4 tCLK
—
Unit
ns
RESET
t wRSL
14