MB86604L Datasheet, PDF (17/56 Pages) Fujitsu Component Limited. – SCSI-II Protocol Controller (with single-ended driver/receiver)

MB86604L
• Register write timing (for external access)
Parameter
Symbol
Base signal
Position*
Address (A0), BHE set up time
WR “L”
tsuAE
A
Address (A0), BHE hold time
WR “H”
thAE
B
CS1 set up time
WR “L”
tsuCS1
C
CS1 hold time
WR “H”
thCS1
D
DMA data bus output delay time
WR “L”
tvDMD
E
DMA data bus output undefined time
WR “H”
tWRDMD
F
MPU data → DMA data bus output delay time
—
tDDMD
G
* : The position number indicates the position in the waveform.
Value
Min.
Max.
40
—
20
—
20
—
10
—
—
70
10
—
—
40
Unit
ns
ns
ns
ns
ns
ns
ns
A0
BHE
A
t suAE
B
t hAE
CS1
C
t suCS1
D
t hCS1
WR
*+456"-!,+6!, ^{D15 to D8, UDP}
D7 to D0, LDP
DMD15 to DMD8, UDMDP
DMD7 to DMD0, LDMDP
E
t vDMD
G
t DDMD
Data
F
t WRDMD
Valid data
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