MB86604L Datasheet, PDF (21/56 Pages) Fujitsu Component Limited. – SCSI-II Protocol Controller (with single-ended driver/receiver)

MB86604L
• Register write timing (for external access)
Parameter
Symbol
Base signal
Position*
Address (A0) set up time
UDS/LDS “L” tsuAE
A
Address (A0) hold time
UDS/LDS “H” thAE
B
CS1 set up time
UDS/LDS “L” tsuCS1
C
CS1 hold time
UDS/LDS “H” thCS1
D
R/W set up time
UDS/LDS “L” tsuRW
E
R/W hold time
UDS/LDS “H” thRW
F
DMA data bus output delay time
UDS/LDS “L” tvDMD
G
DMA data bus output undefined time
UDS/LDS “H” tDSDMD
H
MPU data → DMA data bus output delay time
—
tDDMD
I
* : The position number indicates the position in the waveform.
Value
Min.
Max.
40
—
20
—
20
—
10
—
20
—
20
—
—
70
10
—
—
40
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
A0
A
t suAE
B
t hAE
CS1
C
t suCS1
D
t hCS1
R/W
E
t suRW
F
t hRW
UDS/LDS
'*+23456!,*+56"-!, ^{D15 to D8, UDP}
D7 to D0, LDP
DMD15 to DMD8, UDMDP
DMD7 to DMD0, LDMDP
G
t vDMD
H
t DSDMD
Data
I
t DDMD
Valid data
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