MB86604L Datasheet, PDF (38/56 Pages) Fujitsu Component Limited. – SCSI-II Protocol Controller (with single-ended driver/receiver)

MB86604L
(b) Output timing (target → initiator)
Parameter
Symbol
Base signal
Position*¹
Value
Min.
Max.
ACK “L” assert time
REQ “H” negate time
REQ “L”
tRQAKL
A
ACK “L”
tAKRQH
B
0
—
—
60
ACK “H” negate time
Time from output data valid to
REQ “L” assert *²
REQ “H”
—
tRQAKH
tDBRQ
C
0
—
D
S • tCLK – 10 —
Output data hold time
ACK “L”
thDB
E
2 tCLK
—
REQ “L” assert time
ACK “H”
tAKRQ1
F
—
40
*1: The position number indicates the position in the waveform.
*2: “S” value is based on the asychronous set up time setting register (address 17h).
Note: The output timing definitions are not applied when the data register is EMPTY in the data phase.
Unit
ns
ns
ns
ns
ns
ns
t AKRQ2 ^*
REQ
*+3456?@A!,7ACK
DB7 to DB0
DBP
A
t RQAKL
B
t AKRQH
C
t RQAKH
D
t DBRQ
E
t hDB
Valid data
F
t AKRQ1
D
t DBRQ
Valid data
*: The ACK “L” → REQ “L” time (tAKRQ2) is defined by either longer of (tAKRQH + tRQAKH + tAKRQ1) or (thDB + tDBRQ).
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