MC68HC05P18A Datasheet, PDF (96/130 Pages) Freescale Semiconductor, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
Analog-to-Digital (A/D) Converter
11.7 A/D Conversion Value Data Register
This register contains the output of the A/D converter. See Figure 11-2.
Address: $001D
Bit 7
6
5
4
3
2
1
Bit 0
Read: AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
Write:
Reset:
Unaffected by reset
= Unimplemented
R = Reserved
Figure 11-2. A/D Conversion Value Data Register (ADC)
11.8 A/D Subsystem Operation during Wait Mode and Halt Mode
The A/D subsystem continues normal operation during wait mode and
halt mode. To decrease power consumption during wait or halt, the
ADON bit in the ADSC register and the EERC bit in the EEPROG
register should be cleared if the A/D subsystem is not being used.
11.9 A/D Subsystem Operation during Stop Mode
When stop mode is enabled, execution of the STOP instruction
terminates all A/D subsystem functions. Any pending conversion is
aborted. When the oscillator resumes operation upon leaving the stop
mode, a finite amount of time passes before the A/D subsystem
stabilizes sufficiently to provide conversions at its rated accuracy. The
delays built into the MC68HC05P18A when coming out of stop mode are
sufficient for this purpose. No explicit delays need to be added to the
application software.
Technical Data
Analog-to-Digital (A/D) Converter
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MC68HC05P18A