MC68HC05P18A Datasheet, PDF (78/130 Pages) Freescale Semiconductor, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
Serial Input/Output Ports (SIOP)
application software, these actions could affect the transmitted or
received data.
HCO5 INTERNAL BUS
SPE
76543210
CONTROL
REGISTER
$0A
BAUD
RATE
GENERATOR
76543210
STATUS
REGISTER
$0B
76543210
8-BIT
SDO
SHIFT
REGISTER
SDI
$0C
I/O
CONTROL
LOGIC
SCK
PH2 CLOCK
Figure 9-1. SIOP Block Diagram
SDO/PB5
SDI/PB6
SCK/PB7
9.3 SIOP Signal Format
The SIOP subsystem is software configurable for master or slave
operation. There are no external mode selection inputs available (for
example, slave select pin).
9.3.1 Serial Clock (SCK)
The state of the SCK output normally remains a logic 1 during idle
periods between data transfers. The first falling edge of SCK signals the
beginning of a data transfer. At this time the first bit of received data is
accepted at the SDI pin and the first bit of transmitted data is presented
at the SDO pin (see Figure 9-2). Data is captured at the SDI pin on the
rising edge of SCK, and the first bit of transmitted data is presented at
the SDO pin. The transfer is terminated upon the eighth rising edge of
SCK.
Technical Data
Serial Input/Output Ports (SIOP)
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MC68HC05P18A