MC68HC05P18A Datasheet, PDF (77/130 Pages) Freescale Semiconductor, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
Technical Data — MC68HC05P18A
Section 9. Serial Input/Output Ports (SIOP)
9.1 Contents
9.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
9.3 SIOP Signal Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
9.3.1 Serial Clock (SCK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
9.3.2 Serial Data Input (SDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
9.3.3 Serial Data Output (SDO). . . . . . . . . . . . . . . . . . . . . . . . . . .79
9.4 SIOP Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
9.4.1 SIOP Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
9.4.2 SIOP Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
9.4.3 SIOP Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
9.2 Introduction
The simple synchronous serial input/output (I/O) port (SIOP) subsystem
is designed to provide efficient serial communications between
peripheral devices or other MCUs. The SIOP is implemented as a 3-wire
master/slave system with:
• Serial clock (SCK)
• Serial data input (SDI)
• Serial data output (SDO)
A block diagram of the SIOP is shown in Figure 9-1.
The SIOP subsystem shares its input/output pins with port B. When the
SIOP is enabled, SPE bit set in the SIOP control register (SCR), port B
data direction register (DDR), and data register are modified by the
SIOP. Although port B DDR and data registers can be altered by
MC68HC05P18A
Serial Input/Output Ports (SIOP)
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Technical Data