MC68HC05P18A Datasheet, PDF (70/130 Pages) Freescale Semiconductor, Inc – HCMOS Microcontroller Unit

16-Bit Timer
Freescale Semiconductor, Inc.
8.5 Input Capture
Two 8-bit read-only registers (ICRH and ICRL) make up the 16-bit input
capture. They are used to latch the value of the free-running counter
after a defined transition is sensed by the input capture edge detector.
NOTE: The input capture edge detector contains a Schmitt trigger to improve
noise immunity.
The edge that triggers the counter transfer is defined by the input edge
bit (IEDG) in TCR. Reset does not affect the contents of the input
capture registers. See Figure 8-8.
Address:
Read:
Write:
Reset:
$0014
Bit 7
ICRH7
6
ICRH6
5
ICRH5
4
ICRH4
3
ICRH3
2
ICRH2
Unaffected by reset
1
ICRH1
Bit 0
ICRH0
Address:
Read:
Write:
Reset:
$0015
Bit 7
ICRL7
6
ICRL6
5
ICRL5
4
ICRL4
3
ICRL3
2
ICRL2
1
ICRL1
Unaffected by reset
Figure 8-8. Input Capture Registers (ICRH/ICRL)
Bit 0
ICRL0
The result obtained by an input capture will be one more than the value
of the free-running counter on the rising edge of the PH2 clock preceding
the external transition (see Figure 8-9). This delay is required for internal
synchronization. Resolution is affected by the prescaler, allowing the
free-running counter to increment once every four PH2 clock cycles.
The contents of the free-running counter are transferred to the input
capture registers on each proper signal transition regardless of the state
of the input capture flag bit (ICF) in register TSR. The input capture
registers always contain the free-running counter value which
corresponds to the most recent input capture.
Technical Data
16-Bit Timer
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MC68HC05P18A