MC68HC05P18A Datasheet, PDF (69/130 Pages) Freescale Semiconductor, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
16-Bit Timer
Output Compare
counter increments every four PH2 clock cycles. The minimum time
required to update the output compare registers is a function of software
rather than hardware.
The output compare output level bit (OLVL) will be clocked to its output
latch regardless of the state of the output compare flag bit (OCF). A valid
output compare must occur before the OLVL bit is clocked to its output
latch (TCMP).
Since neither the output compare flag (OCF) nor the output compare
registers are affected by reset, care must be exercised when initializing
the output compare function. This procedure is recommended:
1. Block interrupts by setting the I bit in the condition code register
(CCR).
2. Write the MSB of the output compare register pair (OCRH) to
inhibit further compares until the LSB is written.
3. Read the timer status register (TSR) to arm the output compare
flag (OCF).
4. Write the LSB of the output compare register pair (OCRL) to
enable the output compare function and to clear its flag and
interrupt.
5. Unblock interrupts by clearing the I bit in the CCR.
This procedure prevents the output compare flag bit (OCF) from being
set between the time it is read and the time the output compare registers
are updated. A software example is shown in Figure 8-7.
9B
SEI
BLOCK INTERRUPTS
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B6
XX
LDA
DATAH HI BYTE FOR COMPARE
BE
XX
LDX
DATAL
LOW BYTE FOR COMPARE
B7
16
STA
OCRH
INHIBIT OUTPUT COMPARE
B6
13
LDA
TSR
ARM OCF BIT TO CLEAR
BF
17
STX
OCRL
READY FOR NEXT COMPARE
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Figure 8-7. Output Compare Software Initialization Example
MC68HC05P18A
16-Bit Timer
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Technical Data