MC68HC05P18A Datasheet, PDF (68/130 Pages) Freescale Semiconductor, Inc – HCMOS Microcontroller Unit

16-Bit Timer
Freescale Semiconductor, Inc.
8.4 Output Compare
The output compare function may be used to generate an output
waveform and/or as an elapsed time indicator. All of the bits in the output
compare register pair, OCRH/OCRL, are readable and writable and are
not altered by the 16-bit timer’s control logic. Reset does not affect the
contents of these registers. If the output compare function is not utilized,
its registers may be used for data storage. See Figure 8-6.
Address:
Read:
Write:
Reset:
$0016
Bit 7
OCRH7
6
OCRH6
5
OCRH5
4
3
OCRH4 OCRH3
Unaffected by reset
2
OCRH2
1
OCRH1
Bit 0
OCRH0
Address: $0017
Bit 7
6
5
4
3
2
1
Bit 0
Read:
OCRL7
Write:
OCRL6
OCRL5
OCRL4
OCRL3
OCRL2
OCRL1
OCRL0
Reset:
Unaffected by reset
Figure 8-6. Output Compare Registers (OCRH/OCRL)
The contents of the output compare registers are compared with the
contents of the free-running counter once every four PH2 clock cycles.
If a match is found, the output compare flag bit (OCF) is set and the
output level bit (OLVL) is clocked to the output latch. The values in the
output compare registers and output level bit should be changed after
each successful comparison to control an output waveform or to
establish a new elapsed timeout. An interrupt can also accompany a
successful output compare if the output compare interrupt enable bit
(OCIE) is set.
After a CPU write cycle to the MSB of the output compare register pair
(OCRH), the output compare function is inhibited until the LSB (OCRL)
is written. Both bytes must be written if the MSB is written. A write made
only to the LSB will not inhibit the compare function. The free-running
Technical Data
16-Bit Timer
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MC68HC05P18A