MC68HC05P18A Datasheet, PDF (43/130 Pages) Freescale Semiconductor, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
Interrupts
Interrupt Types
4.4.3 Hardware Interrupts
All hardware interrupts are maskable by the I bit in the CCR. If the I bit
is set, all hardware interrupts (internal and external) are disabled.
Clearing the I bit enables the hardware interrupts.
The four hardware interrupts are explained here:
• External interrupt (IRQ)
• Input capture interrupt
• Output compare interrupt
• Timer overflow interrupt
4.4.3.1 External Interrupt (IRQ)
The IRQ pin drives an asynchronous interrupt to the CPU. An edge
detector flip-flop is latched on the falling edge of IRQ. If either the output
from the internal edge detector flip-flop or the level on the IRQ pin is low,
a request is synchronized to the CPU to generate the IRQ interrupt. If the
edge-sensitive only mask option is selected, the output of the internal
edge detector flip-flop is sampled and the input level on the IRQ pin is
ignored. If port A interrupts are selected as a mask option, a port A
interrupt uses the same vector. The interrupt service routine address is
specified by the contents of memory locations $3FFA and $3FFB.
NOTE:
The internal interrupt latch is cleared 9 PH2 clock cycles after the
interrupt is recognized (after location $3FFA is read). Therefore, another
external interrupt pulse could be latched during the IRQ service routine.
When the edge- and level-sensitive mask option is selected, the voltage
applied to the IRQ pin must return to the high state before the return-
from-interrupt (RTI) instruction in the interrupt service routine is
executed.
4.4.3.2 Input Capture Interrupt
The input capture interrupt is generated by the 16-bit timer as described
in Section 8. 16-Bit Timer. The input capture interrupt flag is located in
MC68HC05P18A
Interrupts
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