MC68HC05P18A Datasheet, PDF (72/130 Pages) Freescale Semiconductor, Inc – HCMOS Microcontroller Unit

16-Bit Timer
Freescale Semiconductor, Inc.
8.6 Timer Control Register
The timer control (TCR) shown in Figure 8-10 and free-running counter
(TMRH, TMRL, ACRH, ACRL) registers are the only registers of the 16-
bit timer affected by reset. The output compare port (TCMP) is forced
low after reset and remains low until OLVL is set and a valid output
compare occurs.
Address:
Read:
Write:
Reset:
$0012
Bit 7
6
5
4
3
2
1
0
0
0
ICIE OCIE TOIE
IEDG
0
0
0
0
0
0
U
= Unimplemented
U = Unaffected
Figure 8-10. Timer Control Register (TCR)
Bit 0
OLVL
0
ICIE — Input Capture Interrupt Enable Bit
Bit 7, when set, enables input capture interrupts to the CPU. The
interrupt will occur at the same time bit 7 (ICF) in the TSR register is
set.
OCIE — Output Comapre Interrupt Enable Bit
Bit 6, when set, enables output compare interrupts to the CPU. The
interrupt will occur at the same time bit 6 (OCF) in the TSR register is
set.
TOIE — Timer Overflow Interrupt Enable Bit
Bit 5, when set, enables timer overflow (rollover) interrupts to the
CPU. The interrupt will occur at the same time bit 5 (TOF) in the TSR
register is set.
IEDG — Input Capture Edge Select Bit
Bit 1 selects which edge of the input capture signal will trigger a
transfer of the contents of the free-running counter registers to the
input capture registers. Clearing this bit will select the falling edge,
setting it selects the rising edge.
Technical Data
16-Bit Timer
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MC68HC05P18A