MC68HC05P18A Datasheet, PDF (67/130 Pages) Freescale Semiconductor, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
16-Bit Timer
Timer
of missing timer overflow interrupts due to clearing of the TOF. See
Figure 8-4.
The free-running counter is initialized to $FFFC during reset and is a
read-only register. During power-on reset (POR), the counter is
initialized to $FFFC and begins counting after the oscillator startup
delay. Since the counter is 16 bits preceded by a fixed divide-by-four
prescaler, the value in the counter repeats every 262,144 PH2 clock
cycles (524,288 oscillator cycles). When the free-running counter rolls
over from $FFFF to $0000, the timer overflow flag bit (TOF) in the timer
status register (TSR) is set. An interrupt can also be enabled when
counter rollover occurs by setting the timer overflow interrupt enable bit
(TOIE) in the timer control register (TCR). See Figure 8-5.
PH2 CLOCK
16-BIT FREE-RUNNING
COUNTER
$FFFE
$FFFF
$0000
$0001
$0002
TIMER OVERFLOW
FLAG (TOF)
Note: The TOF bit is set at timer state T11 (transition of counter from $FFFF to $0000). It is cleared by reading the timer
status register (TSR) during the high portion of the PH2 clock followed by reading the LSB of the counter register
pair (TCRL).
Figure 8-4. State Timing Diagram for Timer Overflow
PH2 CLOCK
INTERNAL RESET
16-BIT FREE-RUNNING
COUNTER
RESET
(EXTERNAL OR OTHER)
$FFFC
$FFFD
$FFFE
Note: The counter and control registers are the only 16-bit timer registers affected by reset.
Figure 8-5. State Timing Diagram for Timer Reset
MC68HC05P18A
16-Bit Timer
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$FFFF
Technical Data