MC68HC05P18A Datasheet, PDF (19/130 Pages) Freescale Semiconductor, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
General Description
Mask Options
1.4 Mask Options
The MC68HC05P18A has eight mask options:
1. IRQ is edge- and level-sensitive or edge-sensitive only.
2. SIOP MSB (most-significant bit) first or LSB (least-significant bit)
first
3. SIOP clock rate set to OSC divided by 2, 4, 8, 16, 32, 64, 128, or
256
4. COP watchdog timer enabled or disabled
5. Stop instruction enabled or converted to halt mode
6. Option to enable clock output pin to replace PD5
7. Option to individually enable pullups/interrupts on each of the
eight port A pins
8. LVR enabled or disabled
1.5 Functional Pin Description
This subsection describes the functionality of each pin on the
MC68HC05P18A package.
NOTE:
For pins connected to subsystems described in other sections, a
reference to the section is given instead of a detailed functional
description.
The pinout is shown in Figure 1-2.
MC68HC05P18A
General Description
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Technical Data