MC68HC05P18A Datasheet, PDF (71/130 Pages) Freescale Semiconductor, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
16-Bit Timer
Input Capture
After a read of the MSB of the input capture register pair (ICRH), counter
transfers are inhibited until the LSB of the register pair (ICRL) is also
read. This characteristic forces the minimum pulse period attainable to
be determined by the time required to execute an input capture software
routine in an application.
Reading the LSB of the input capture register pair (ICRL) does not inhibit
transfer of the free-running counter. Again, minimum pulse periods are
ones which allow software to read the LSB of the register pair (ICRL) and
perform needed operations. There is no conflict between reading the
LSB (ICRL) and the free-running counter transfer since they occur on
opposite edges of the PH2 clock.
PH2 CLOCK
16-BIT FREE-RUNNING _$FFEB
COUNTER
TCAP PIN
$FFEC
$FFED
$FFEE
$FFEF
INPUT CAPTURE
LATCH
INPUT CAPTURE
REGISTER
(SEE NOTE)
$FFED
INPUT CAPTURE
FLAG
Note: If the input edge occurs in the shaded area from one T10 timer state to the other T10 timer state, the input capture
flag is set during the next T11 timer state.
Figure 8-9. State Timing Diagram for Input Capture
MC68HC05P18A
16-Bit Timer
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Technical Data