MC68HC05P18A Datasheet, PDF (73/130 Pages) Freescale Semiconductor, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
16-Bit Timer
Timer Status Register
OLVL — Output Compare Output Level Select Bit
Bit 0 selects the output level (high or low) that is clocked into the
output compare output latch at the next successful output compare.
8.7 Timer Status Register
Reading the timer status register (TSR) satisfies the first condition
required to clear status flags and interrupts (see Figure 8-11). The only
remaining step is to read (or write) the register associated with the active
status flag (and/or interrupt). This method does not present any
problems for input capture or output compare functions.
However, a problem can occur when using a timer interrupt function and
reading the free-running counter at random times to, for example,
measure an elapsed time. If the proper precautions are not designed into
the application software, a timer interrupt flag (TOF) could
unintentionally be cleared if:
1. The TSR is read when bit 5 (TOF) is set.
2. The LSB of the free-running counter is read, but not for the
purpose of servicing the flag or interrupt.
The alternate counter registers (ACRH and ACRL) contain the same
values as the timer registers (TMRH and TMRL). Registers ACRH and
ACRL can be read at any time without affecting the timer overflow flag
(TOF) or interrupt.
Address: $0013
Bit 7
6
5
4
3
2
1
Bit 0
Read: ICF
OCF
TOF
0
0
0
0
0
Write:
Reset: U
U
U
0
0
0
0
0
= Unimplemented
U = Unaffected
Figure 8-11. Timer Status Register (TSR)
MC68HC05P18A
16-Bit Timer
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Technical Data