MC68HC05P18A Datasheet, PDF (74/130 Pages) Freescale Semiconductor, Inc – HCMOS Microcontroller Unit

16-Bit Timer
Freescale Semiconductor, Inc.
ICF — Input Capture Flag
Bit 7 is set when the edge specified by IEDG in register TCR has been
sensed by the input capture edge detector fed by pin TCAP. This flag,
and the input capture interrupt, can be cleared by reading register
TSR followed by reading the LSB of the input capture register pair
(ICRL).
OCF — Output Compare Bit
Bit 6 is set when the contents of the output compare registers match
the contents of the free-running counter. This flag, and the output
compare interrupt, can be cleared by reading register TSR followed
by writing the LSB of the output compare register pair (OCRL).
TOF — Timer Overflow Flag
Bit 5 is set by a rollover of the free-running counter from $FFFF to
$0000. This flag, and the timer overflow interrupt, can be cleared by
reading register TSR followed by reading the LSB of the timer register
pair (TMRL).
8.8 Timer Operation during Wait Mode and Halt Mode
During wait mode and halt mode the 16-bit timer continues to operate
normally and may generate an interrupt to trigger the MCU out of the wait
mode and halt mode.
8.9 Timer Operating during Stop Mode
When the MCU enters the stop mode, the free-running counter stops
counting. (The PH2 clock is stopped.) It remains at that particular count
value until the stop mode is exited by applying a low signal to the IRQ
pin, at which time the counter resumes from its stopped value as if
nothing had happened. If stop mode is exited via an external RESET
(logic low applied to the RESET pin), the counter is forced to $FFFC.
If a valid input capture edge occurs at the TCAP pin during stop mode,
the input capture detect circuitry is armed. This action does not set any
flags or wake up the MCU, but when the MCU does wake up there will
Technical Data
16-Bit Timer
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MC68HC05P18A