MC68HC05P18A Datasheet, PDF (48/130 Pages) Freescale Semiconductor, Inc – HCMOS Microcontroller Unit

Resets
Freescale Semiconductor, Inc.
5.4.3 Low-Voltage Reset (LVR)
The internal LVR reset is generated when the supply voltage to the V_DD
pin falls below a nominal 3.80 Vdc. The LVR threshold is not intended to
be an accurate and stable trip point, but is intended to assure that the
CPU is held in reset when the V_DD supply voltage is below reasonable
operating limits. If the LVR is tripped for a short time, the LVR reset
signal will last at least two cycles of the CPU bus clock, PH2. A mask
option is provided to disable the LVR.
The LVR generates the RST signal, which resets the CPU and other
peripherals. If any other reset function is active at the end of the LVR
reset signal, the RST signal remains in the reset condition until the other
reset condition(s) end.
Technical Data
Resets
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MC68HC05P18A