MC68HC05C8A Datasheet, PDF (95/116 Pages) Motorola, Inc – Microcontrollers

13.11 3.3-V Serial Peripheral Interface Timing
3.3-V Serial Peripheral Interface Timing
Num
Characteristic⁽¹⁾
Symbol
Min
Max Unit
Operating frequency
Master
Slave
f_OP(M)
f_OP(S)
dc
0.5
f_OP
dc
1.0
MHz
Cycle time
1
Master
Slave
t_CYC(M)
t_CYC(S)
2.0
—
t_CYC
1.0
—
µs
Enable lead time
2
Master
Slave
t_Lead(M)
(2)
—
ns
t_Lead(S)
500
—
Enable lag time
3
Master
Slave
t_Lag(M)
t_Lag(S)
(2)
—
ns
1.5
—
µs
Clock (SCK) high time
4
Master
Slave
t_W(SCKH)M
720
t_W(SCKH)S
400
—
ns
—
Clock (SCK) low time
5
Master
Slave
t_W(SCKL)M
720
t_W(SCKL)S
400
—
ns
—
Data setup time (inputs)
6
Master
Slave
t_SU(M)
t_SU(S)
200
—
ns
200
—
Data hold time (inputs)
7
Master
Slave
8 Slave access time (time to data active from high-impedance state)
9 Slave disable time (hold time to high-impedance state)
Data valid
10
Master (before capture edge)
Slave (after enable edge)⁽³⁾
t_H(M)
t_H(S)
t_A
t_DIS
t_V(M)
t_V(S)
200
200
0
—
0.25
—
—
ns
—
250
ns
500
ns
—
t_CYC(M)
500
ns
Data hold time (outputs)
11
Master (after capture edge)
Slave (after enable edge)
t_HO(M)
t_HO(S)
0.25
0
—
t_CYC(M)
—
ns
Rise time (20% V_DD to 70% V_DD, C_L = 200 pF)
12
SPI outputs (SCK, MOSI, and MISO)
SPI Inputs (SCK, MOSI, MISO, and SS)
t_RM
—
200
ns
t_RS
—
2.0
µs
Fall time (70% V_DD to 20% V_DD, C_L = 200 pF)
13
SPI outputs (SCK, MOSI, and MISO)
SPI inputs (SCK, MOSI, MISO, and SS)
t_FM
—
200
ns
t_FS
—
2.0
µs
1. V_DD = 3.3 Vdc ± 0.3 Vdc; V_SS = 0 Vdc, T_A = T_L to T_H. Refer to Figure 13-9 and Figure 13-10 for timing diagrams.
2. Signal production depends on software.
3. Assumes 200 pF load on all SPI pins
MC68HC05C8A • MC68HCL05C8A • MC68HSC05C8A Data Sheet, Rev. 5.1
Freescale Semiconductor
95