MC68HC05C8A Datasheet, PDF (61/116 Pages) Motorola, Inc – Microcontrollers

Functional Description
10.4 Functional Description
Figure 10-2 shows a block diagram of the SPI circuitry. When a master device transmits data to a slave
via the MOSI line, the slave device responds by sending data to the master device via the master’s MISO
line. This implies full duplex transmission with both data out and data in synchronized with the same clock
signal. Thus, the byte transmitted is replaced by the byte received and eliminates the need for separate
transmit-empty and receive-full status bits. A single status bit (SPIF) is used to signify that the input/output
(I/O) operation has been completed.
INTERNAL
MCU CLOCK
DIVIDER
÷ 2 ÷ 4 ÷ 16 ÷ 32
S
M
MSB
LSB
M
8-BIT SHIFT REG
S
READ DATA BUFF
SELECT
SPI CLOCK
(MASTER)
CLOCK
S
CLOCK
LOGIC
M
MISO
PD2
MOSI
PD3
SCK
PD4
SS
PD5
SPI CONTROL
MSTR
SPE
SPI STATUS REGISTER
SPI CONTROL REGISTER
INTERNAL
DATA BUS
SPI INTERRUPT
REQUEST
Figure 10-2. Serial Peripheral Interface Block Diagram
MC68HC05C8A • MC68HCL05C8A • MC68HSC05C8A Data Sheet, Rev. 5.1
Freescale Semiconductor
61