MC68HC05C8A Datasheet, PDF (23/116 Pages) Motorola, Inc – Microcontrollers

Random-Access Memory (RAM)
Addr.
$0000
$0001
$0002
$0003
$0004
$0005
$0006
$0007
↓
$0009
Register Name
Port A Data Register
(PORTA)
See page 37.
Port B Data Register
(PORTB)
See page 37.
Port C Data Register
(PORTC)
See page 38.
Port D Data Register
(PORTD)
See page 38.
Port A Data Direction Register
(DDRA)
See page 37.
Port B Data Direction Register
(DDRB)
See page 37.
Port C Data Direction Register
(DDRC)
See page 38.
Read:
Write:
Reset
Read:
Write:
Reset
Read:
Write:
Reset
Read:
Write:
Reset
Read:
Write:
Reset
Read:
Write:
Reset
Read:
Write:
Reset
Bit 7
PA7
PB7
PC7
PD7
DDRA7
0
DDRB7
0
DDRC7
0
6
PA6
PB6
PC6
DDRA6
0
DDRB6
0
DDRC6
0
5
PA5
PB5
PC5
PD5
DDRA5
0
DDRB5
0
DDRC5
0
4
3
PA4
PA3
Unaffected by reset
PB4
PB3
Unaffected by reset
PC4
PC3
Unaffected by reset
PD4
PD3
Unaffected by reset
DDRA4 DDRA3
0
0
DDRB4 DDRB3
0
0
DDRC4 DDRC3
0
0
Unimplemented
2
1
Bit 0
PA2
PA1
PA0
PB2
PB1
PB0
PC2
PC1
PC0
PD2
PD1
PD0
DDRA2 DDRA1 DDRA0
0
0
0
DDRB2 DDRB1 DDRB0
0
0
0
DDRC2 DDRC1 DDRC0
0
0
0
$000A
$000B
$000C
$000D
SPI Control Register
(SPCR)
See page 63.
SPI Status Register
(SPSR)
See page 64.
SPI Data Register
(SPDR)
See page 65.
SCI Baud Rate Register
BAUD
See page 57.
Read:
Write:
Reset
Read:
Write:
Reset
Read:
Write:
Reset
Read:
Write:
Reset
SPIE
0
SPIF
0
SPD7
0
0
SPE
0
WCOL
0
SPD6
0
0
0
SPD5
0
SCP1
0
0
= Unimplemented
MSTR
CPOL
CPHA SPR1 SPR0
0
0
0
MODF
0
U
U
0
0
0
0
0
0
U
U
SPD4
SPD31
SPD2 SPD1 SPD0
Unaffected by reset
SCP0
0
SCR2 SCR1 SCR0
0
0
U
U
U
R = Reserved
U = Unaffected
Figure 2-2. Input/Output Registers (Sheet 1 of 3)
MC68HC05C8A • MC68HCL05C8A • MC68HSC05C8A Data Sheet, Rev. 5.1
Freescale Semiconductor
23