MC68HC05C8A Datasheet, PDF (62/116 Pages) Motorola, Inc – Microcontrollers

Serial Peripheral Interface (SPI)
The SPI data register (SPDR) is double buffered on read, but not on write. If a write is performed during
data transfer, the transfer occurs uninterrupted, and the write will be unsuccessful. This condition will
cause the write collision (WCOL) status bit in the SPSR to be set. After a data byte is shifted, the SPIF
flag of the SPSR is set.
In the master mode, the SCK pin is an output. It idles high or low, depending on the CPOL bit in the SPCR,
until data is written to the shift register, at which point eight clocks are generated to shift the eight bits of
data and then SCK goes idle again.
In a slave mode, the slave select start logic receives a logic low at the SS pin and a clock at the SCK pin.
Thus, the slave is synchronized with the master. Data from the master is received serially at the MOSI
line and loads the 8-bit shift register. After the 8-bit shift register is loaded, its data is parallel transferred
to the read buffer. During a write cycle, data is written into the shift register, then the slave waits for a clock
train from the master to shift the data out on the slave’s MISO line.
Figure 10-3 illustrates the MOSI, MISO, SCK, and SS master-slave interconnections.
SPI SHIFT REGISTER
PD3/MOSI
PD2/MISO
PD5
I/O PORT
SS
SPDR ($000C)
PD4/SCK
SPI SHIFT REGISTER
SPDR ($000C)
MASTER MCU
SLAVE MCU
Figure 10-3. Serial Peripheral Interface Master-Slave Interconnection
10.5 SPI Registers
This subsection describes the three registers in the SPI which provide control, status, and data storage
functions. These registers are:
• Serial peripheral control register (SPCR)
• Serial peripheral status register (SPSR)
• Serial peripheral data I/O register (SPDR)
MC68HC05C8A • MC68HCL05C8A • MC68HSC05C8A Data Sheet, Rev. 5.1
62
Freescale Semiconductor