MC68HC05C8A Datasheet, PDF (45/116 Pages) Motorola, Inc – Microcontrollers

Timer Control Register
8.5 Timer Control Register
The timer control register (TCR) is a read/write register containing five control bits. Three bits control
interrupts associated with the timer status register flags ICF, OCF, and TOF.
Address: $0012
Bit 7
6
5
4
3
2
1
Bit 0
Read:
ICIE
OCIE
TOIE
0
0
0
IEDG
OLVL
Write:
Reset: 0
0
0
0
0
0
U
0
U = Unaffected
Table 8-1. Timer Control Register (TCR)
ICIE — Input Capture Interrupt Enable Bit
1 = Interrupt enabled
0 = Interrupt disabled
OCIE — Output Compare Interrupt Enable Bit
1 = Interrupt enabled
0 = Interrupt disabled
TOIE — Timer Overflow Interrupt Enable Bit
1 = Interrupt enabled
0 = Interrupt disabled
IEDG — Input Edge Bit
Value of input edge determines which level transition on TCAP pin will trigger free-running counter
transfer to the input capture register.
1 = Positive edge
0 = Negative edge
Reset does not affect the IEDG bit.
OLVL — Output Level Bit
Value of output level is clocked into output level register by the next successful output compare and
will appear on the TCMP pin.
1 = High output
0 = Low output
Bits 2, 3, and 4 — Not used
Always read 0
MC68HC05C8A • MC68HCL05C8A • MC68HSC05C8A Data Sheet, Rev. 5.1
Freescale Semiconductor
45