English
Language : 

MC68HC05C8A Datasheet, PDF (94/116 Pages) Motorola, Inc – Microcontrollers
◁
Electrical Specifications
13.10 5.0-V Serial Peripheral Interface Timing
Num
Characteristic(1)
Symbol
Min
Max
Operating frequency
Master
Slave
fOP(M)
fOP(S)
dc
0.5
dc
2.1
Cycle time
1
Master
Slave
tCYC(M)
2.0
—
tCYC(S)
480
—
Enable lead time
2
Master
Slave
tLead(M)
(2)
—
tLead(S)
240
—
Enable lag time
3
Master
Slave
tLag(M)
tLag(S)
(2)
—
720
—
Clock (SCK) high time
4
Master
Slave
tW(SCKH)M
340
—
tW(SCKH)S
190
—
Clock (SCK) low time
5
Master
Slave
tW(SCKL)M
340
—
tW(SCKL)S
190
—
Data setup time (inputs)
6
Master
Slave
tSU(M)
tSU(S)
100
—
100
—
Data hold time (inputs)
7
Master
Slave
8
Slave access time (time-to-data active from high-impedance
state)
tH(M)
tH(S)
tA
100
—
100
—
0
120
9 Slave disable time (hold time to high-impedance state)
Data valid
10
Master (before capture edge)
Slave (after enable edge)(3)
tDIS
tV(M)
tV(S)
—
240
0.25
—
—
240
Data hold time (outputs)
11
Master (after capture edge)
Slave (after enable edge)
Rise time (20% VDD to 70% VDD, CL = 200 pF)
12
SPI outputs (SCK, MOSI, and MISO)
SPI inputs (SCK, MOSI, MISO, and SS)
Fall time (70% VDD to 20% VDD, CL = 200 pF)
13
SPI outputs (SCK, MOSI, and MISO)
SPI inputs (SCK, MOSI, MISO, and SS)
tHO(M)
tHO(S)
tRM
tRS
tFM
tFS
0.25
—
0
—
—
100
—
2.0
—
100
—
2.0
1. VDD = 5.0 Vdc ± 10%; VSS = 0 Vdc, TA = TL to TH. Refer to Figure 13-9 and Figure 13-10 for timing diagrams.
2. Signal production depends on software.
3. Assumes 200 pF load on all SPI pins
Unit
fOP
MHz
tCYC
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCYC(M)
ns
tCYC(M)
ns
ns
µs
ns
µs
MC68HC05C8A • MC68HCL05C8A • MC68HSC05C8A Data Sheet, Rev. 5.1
94
Freescale Semiconductor
 ▷