MC68HC05C8A Datasheet, PDF(92/116 Page) Motorola, Inc

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MC68HC05C8A Datasheet, PDF (92/116 Pages) Motorola, Inc – Microcontrollers

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Electrical Specifications

IRQ PIN

tILIL

tILIH

a. Edge-Sensitive Trigger Condition. The minimum pulse width (tILIH) is either 125 ns (fOP = 2.1 MHz)

or 250 ns (fOP = 1 MHz). The period tILIL should not be less than the number of tCYC cycles it takes to

execute the interrupt service routine plus 19 tCYC cycles.

IRQ1

tILIH

NORMALLY USED

WITH WIRED-OR

IRQn

CONNECTION

IRQ

(INTERNAL)

b. Level-Sensitive Trigger Condition. If after servicing an interrupt the IRQ remains low, the

next interrupt is recognized.

Figure 13-5. External Interrupt Timing

INTERNAL

CLOCK(1)

INTERNAL

ADDRESS BUS(1)

INTERNAL

DATA BUS(1)

RESET(2)

1FFE

1FFF

NEW PC

NEW

PCH

PCL

CODE

tRL

Notes:

1. Internal clock, internal address bus, and internal data bus are not available externally.

2. The next rising edge of the internal clock after the rising edge of RESET initiates the reset sequence.

Figure 13-6. External Reset Timing

MC68HC05C8A â¢ MC68HCL05C8A â¢ MC68HSC05C8A Data Sheet, Rev. 5.1

Freescale Semiconductor

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