MC68HC05C8A Datasheet, PDF (48/116 Pages) Motorola, Inc – Microcontrollers

Serial Communications Interface (SCI)
9.4 SCI Operation
The SCI allows full-duplex, asynchronous, RS232 or RS422 serial communication between the MCU and
remote devices, including other MCUs. The SCI’s transmitter and receiver operate independently,
although they use the same baud-rate generator. This subsection describes the operation of the SCI
transmitter and receiver.
9.4.1 Transmitter
Figure 9-2 shows the structure of the SCI transmitter.
9.4.1.1 Character Length
The transmitter can accommodate either 8-bit or 9-bit data. The state of the M bit in SCI control register 1
(SCCR1) determines character length. When transmitting 9-bit data, bit T8 in SCCR1 is the ninth bit
(bit 8).
9.4.1.2 Character Transmission
During transmission, the transmit shift register shifts a character out to the PD1/TDO pin. The SCI data
register (SCDR) is the write-only buffer between the internal data bus and the transmit shift register.
Writing a logic 1 to the TE bit in SCI control register 2 (SCCR2) and then writing data to the SCDR begins
the transmission. At the start of a transmission, transmitter control logic automatically loads the transmit
shift register with a preamble of logic 1s. After the preamble shifts out, the control logic transfers the
SCDR data into the shift register. A logic 0 start bit automatically goes into the least significant bit position
of the shift register, and a logic 1 stop bit goes into the most significant bit position.
When the data in the SCDR transfers to the transmit shift register, the transmit data register empty
(TDRE) flag in the SCI status register (SCSR) becomes set. The TDRE flag indicates that the SCDR can
accept new data from the internal data bus.
When the shift register is not transmitting a character, the PD1/TDO pin goes to the idle condition, logic 1.
If software clears the TE bit during the idle condition, and while TDRE is set, the transmitter relinquishes
control of the PD1/TDO pin.
9.4.1.3 Break Characters
Writing a logic 1 to the SBK bit in SCCR2 loads the shift register with a break character. A break character
contains all logic 0s and has no start and stop bits. Break character length depends on the M bit in
SCCR1. As long as SBK is at logic 1, transmitter logic continuously loads break characters into the shift
register. After software clears the SBK bit, the shift register finishes transmitting the last break character
and then transmits at least one logic 1. The automatic logic 1 at the end of a break character is to
guarantee the recognition of the start bit of the next character.
9.4.1.4 Idle Characters
An idle character contains all logic 1s and has no start or stop bits. Idle character length depends on the
M bit in SCCR1. The preamble is a synchronizing idle character that begins every transmission.
MC68HC05C8A • MC68HCL05C8A • MC68HSC05C8A Data Sheet, Rev. 5.1
48
Freescale Semiconductor