MC68HC05C8A Datasheet, PDF (111/116 Pages) Motorola, Inc – Microcontrollers

B.6 4.5-V to 5.5-V High-Speed SPI Timing
The data in 13.10 5.0-V Serial Peripheral Interface Timing applies to the MC68HSC05C8A with the
exceptions given here.
Num
Operating frequency
Master
Slave
Characteristic
Cycle time
1
Master
Slave
Enable lead time
2
Master
Slave
Enable lag time
3
Master
Slave
Clock (SCK) high time
4
Master
Slave
Clock (SCK) low time
5
Master
Slave
Data setup time (inputs)
6
Master
Slave
Data hold time (inputs)
7
Master
Slave
8 Slave access time (time to data active from high-impedance state)
9 Slave disable time (hold time to high-impedance state)
Data valid
10 ^{Master (before capture edge)}
Slave (after enable edge)⁽²⁾
Data hold time (outputs)
11 Master (after capture edge)
Slave (After Enable Edge)
Rise time (20% V_DD to 70% V_DD, C_L = 200 pF)
12 SPI outputs (SCK, MOSI, and MISO)
SPI inputs (SCK, MOSI, MISO, and SS)
Fall time (70% V_DD to 20% V_DD, C_L = 200 pF)
13 SPI outputs (SCK, MOSI, and MISO)
SPI inputs (SCK, MOSI, MISO, and SS)
1. Signal production depends on software.
2. Assumes 200 pF load on all SPI pins.
Symbol Min Max Unit
f_OP(M)
f_OP(S)
dc 0.5
f_OP
dc 4.1 MHz
t_CYC(M)
t_CYC(S)
2.0 —
244 —
t_CYC
ns
t_Lead(M)
(1)
—
ns
t_Lead(S)
122 ^—
ns
t_Lag(M)
(1)
—
ns
t_Lag(S)
366 —
ns
t_{W(SCKH)M 166 —}
ns
t_W(SCKH)S 93
—
ns
t_{W(SCKL)M 166 —}
ns
t_W(SCKL)S
93
—
ns
t_SU(M)
49 —
ns
t_SU(S)
49 —
ns
t_H(M)
t_H(S)
t_A
t_DIS
49 —
ns
49 —
ns
0 61
ns
— 122
ns
t_V(M)
t_V(S)
0.25 — t_CYC(M)
— 122
ns
t_HO(M)
t_HO(S)
0.25 — t_CYC(M)
0—
ns
t_RM
— 50
ns
t_RS
— 1.0
µs
t_FM
— 50
ns
t_FS
— 1.0
µs
MC68HC05C8A • MC68HCL05C8A • MC68HSC05C8A Data Sheet, Rev. 5.1
Freescale Semiconductor
111