MC68HC05C8A Datasheet, PDF (30/116 Pages) Motorola, Inc – Microcontrollers

Interrupts
Table 4-1. Vector Addresses for Interrupts and Reset
Register
N/A
N/A
N/A
TSR
TSR
TSR
SCSR
SCSR
SCSR
SCSR
SCSR
SPSR
SPSR
Flag Name
N/A
N/A
N/A
ICF
OCF
TOF
TDRE
TC
RDRF
IDLE
OR
SPIF
MODF
Interrupts
Reset
Software
External interrupt
Timer input capture
Timer output compare
Timer overflow
Transmit buffer empty
Transmit complete
Receiver buffer full
Idle line detect
Overrun
Transfer complete
Mode fault
CPU Interrupt
RESET
SWI
IRQ
TIMER
TIMER
TIMER
SCI
SCI
SCI
SCI
SCI
SPI
SPI
Vector Address
$1FFE–$1FFF
$1FFC–$1FFD
$1FFA–$1FFB
$1FF8–$1FF9
$1FF8–$1FF9
$1FF8–$1FF9
$1FF6–$1FF7
$1FF6–$1FF7
$1FF6–$1FF7
$1FF6–$1FF7
$1FF6–$1FF7
$1FF4–$1FF5
$1FF4–$1FF5
4.3 Software Interrupt (SWI)
The software interrupt (SWI) is an executable instruction and a non-maskable interrupt. It is executed
regardless of the state of the I bit in the CCR. If the I bit is 0 (interrupts enabled), SWI executes after
interrupts which were pending when the SWI was fetched but before interrupts generated after the SWI
was fetched. The interrupt service routine address is specified by the contents of memory locations
$1FFC and $1FFD.
4.4 External Interrupt (IRQ)
If the interrupt mask bit (I bit) of the CCR is set, all maskable interrupts (internal and external) are disabled.
Clearing the I bit enables interrupts. The interrupt request is latched immediately following the falling edge
of IRQ. It is then synchronized internally and serviced as specified by the contents of $1FFA and $1FFB.
When any of the port B pullups are enabled, that pin becomes an additional external interrupt source
which is coupled to the IRQ pin logic. It follows the same edge/edge-level selection that the IRQ pin has.
See Figure 7-1. Port B Pullup Option.
Either a level-sensitive and edge-sensitive trigger, or an edge-sensitive-only trigger operation is
selectable by mask option.
NOTE
The internal interrupt latch is cleared in the first part of the interrupt service
routine; therefore, one external interrupt pulse could be latched and
serviced as soon as the I bit is cleared.
MC68HC05C8A • MC68HCL05C8A • MC68HSC05C8A Data Sheet, Rev. 5.1
30
Freescale Semiconductor