MC68HC05C8A Datasheet, PDF (42/116 Pages) Motorola, Inc – Microcontrollers

Timer
HIGH
BYTE
LOW
BYTE
$16
OUTPUT
$17 ^COMPARE
REGISTER
INTERNAL BUS
INTERNAL
PROCESSOR
CLOCK
8-BIT
BUFFER
÷4
HIGH
BYTE
LOW
BYTE
16-BIT FREE
RUNNING
$18
COUNTER
$19
HIGH LOW
BYTE BYTE
INPUT
$14
CAPTURE _$15
REGISTER
COUNTER _$1A
ALTERNATE _$1B
REGISTER
OUTPUT
COMPARE
CIRCUIT
OVERFLOW
DETECT
CIRCUIT
EDGE
DETECT
CIRCUIT
TIMER _{ICF OCF TOF} $13
STATUS
REGISTER
OUTPUT
LEVEL
REGISTER
DQ
CLK
C
ICIE OCIE
TOIE IEDG OLVL
TIMER
CONTROL
REGISTER
$12
RESET
INTERRUPT
CIRCUIT
OUTPUT
LEVEL
(TCMP)
EDGE
INPUT
(TCAP)
Figure 8-1. Timer Block Diagram
The free-running counter is configured to $FFFC during reset and is always a read-only register. During
a power-on reset, the counter is also preset to $FFFC and begins running after the oscillator start-up
delay. Because the free-running counter is 16 bits preceded by a fixed divide-by-four prescaler, the value
in the free-running counter repeats every 262,144 internal bus clock cycles. When the counter rolls over
from $FFFF to $0000, the TOF bit is set. An interrupt can also be enabled whenever counter rollover
occurs by setting its interrupt enable bit (TOIE).
MC68HC05C8A • MC68HCL05C8A • MC68HSC05C8A Data Sheet, Rev. 5.1
42
Freescale Semiconductor