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MC68HC05C8A Datasheet, PDF (32/116 Pages) Motorola, Inc – Microcontrollers
Interrupts
4.5 Timer Interrupt
Three different timer interrupt flags cause a timer interrupt whenever they are set and enabled. The
interrupt flags are in the timer status register (TSR), and the enable bits are in the timer control register
(TCR). Any of these interrupts will vector to the same interrupt service routine, located at the address
specified by the contents of memory locations $1FF8 and $1FF9.
4.6 Serial Communications Interrupt (SCI)
Five different SCI interrupt flags cause an SCI interrupt whenever they are set and enabled. The interrupt
flags are in the SCI status register (SCSR), and the enable bits are in the SCI control register 2 (SCCR2).
Any of these interrupts will vector to the same interrupt service routine, located at the address specified
by the contents of memory locations $1FF6 and $1FF7.
4.7 Serial Peripheral Interrupt (SPI)
Two different SPI interrupt flags cause an SPI interrupt whenever they are set and enabled. The interrupt
flags are in the SPI status register (SPSR), and the enable bits are in the SPI control register (SPCR).
Either of these interrupts will vector to the same interrupt service routine, located at the address specified
by the contents of memory locations $1FF4 and $1FF5.
MC68HC05C8A • MC68HCL05C8A • MC68HSC05C8A Data Sheet, Rev. 5.1
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Freescale Semiconductor