PXR40 Datasheet, PDF (91/100 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Electrical characteristics
Table 37. DSPI timing^{1 2} (continued)
Spec
Characteristic
Peripheral Bus Freq: 132 MHz
Symbol
Unit
Min
Max
9 Data Setup Time for Inputs
Master (MTFE = 0)
Slave
Master (MTFE = 1, CPHA = 0)⁸
Master (MTFE = 1, CPHA = 1)
t_SUI
20
4
6
20
—
ns
—
ns
—
ns
—
ns
10 Data Hold Time for Inputs
Master (MTFE = 0)
Slave
Master (MTFE = 1, CPHA = 0)⁸
Master (MTFE = 1, CPHA = 1)
t_HI
–3
7
12
–3
—
ns
—
ns
—
ns
—
ns
11 Data Valid (after SCK edge)
Master (MTFE = 0)
Slave
Master (MTFE = 1, CPHA = 0)
Master (MTFE = 1, CPHA = 1)
t_SUO
—
—
—
—
5
ns
25
ns
13
ns
5
ns
12 Data Hold Time for Outputs
Master (MTFE = 0)
Slave
Master (MTFE = 1, CPHA = 0)
Master (MTFE = 1, CPHA = 1)
t_HO
–5
2.5
3
–5
—
ns
—
ns
—
ns
—
ns
1 _{DSPI timing specified at VDD = 1.08 V to 1.32 V, VDDEH = 3.0 V to 5.5 V, VDD33 and VDDSYN = 3.0 V to 3.6 V, and TA = TL to TH}
2 _{Speed is the nominal maximum frequency of platform clock (fplatf). Max speed is the maximum speed allowed including}
frequency modulation (FM). 270 MHz parts allow for 264 Mhz for system core clock (f_sys) + 2% FM.
3 _{The minimum DSPI Cycle Time restricts the baud rate selection for given system clock rate. These numbers are calculated}
based on two devices communicating over a DSPI link.
4 _{The actual minimum SCK cycle time is limited by pad performance.}
5 _{The maximum value is programmable in DSPI_CTARn[PSSCK] and DSPI_CTARn[CSSCK].}
6 _{The maximum value is programmable in DSPI_CTARn[PASC] and DSPI_CTARn[ASC].}
7 _{For example, external master should start SCK clock not earlier than 3 system clock periods after assertion SS}
8 _{This number is calculated assuming the SMPL_PT bitfield in DSPI_MCR is set to 0b10.}
The DSPI in this device can be configured to serialize data to an external device that implements the Microsecond Bus protocol.
DSPI pins support 5 V logic levels or Low Voltage Differential Signalling (LVDS) for data and clock signals to improve high
speed operation.
Table 38. DSPI LVDS timing^{1, 2}
Characteristic
Symbol
Min
Max
Unit
LVDS Clock to Data/Chip Select Outputs
t_LVDSDATA
–0.25 ×
+0.25 ×
ns
t_SCYC
t_SCYC
1 _{These are typical values that are estimated from simulation.}
2 _{See DSPI LVDS Pad related data in Table 14.}
PXR40 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
91