PXR40 Datasheet, PDF (5/100 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

2 PXR40 block diagram
Figure 1 shows a top-level block diagram of the PXR40 microcontrollers.
PXR40 Block Diagram
System
Integration
SPE2
Osc/PLL
Interrupt
Controller
Data and Instruction System
2 x eDMA
64- and
32-ch
e200z7
Superscalar
CPU
FlexRay™
Controller
PXR40 block diagram
Debug
JTAG
Nexus
IEEE
ISTO
5001™-2003
Crossbar Switch (XBAR)
Memory Protection Unit (MPU)
PBRIDGE A
SIU
4 MB
Flash
w/ECC
256 KB
SRAM
w/ECC
(32 KB S/B)
Main Memory System
Timed I/O System
PBRIDGE B
Boot Assist
Module
(BAM)
Communications
eMIOS
32-ch
eTPU2
32-ch
6K
Data
24K
Code
RAM
eTPU2
32-ch
4x
CAN
3x
UART/
LIN
4x
SPI
4x
Dec
Fil
64-ch
QUAD
ADCi
ADC – Analog-to-digital converter
ADCi – ADC interface
AIPS – Peripheral I/O bridge
AMux – Analog multiplexer
CAN – Controller area network
DECFIL– Decimation filter
EBI – External bus interface
ECSM – Error correction status module
eDMA2 – Enhanced direct memory access
eMIOS – Enhanced modular I/O system
eQADC – Enhanced queued A/D converter module
eTPU2 – Enhanced time processing unit 2
MMU
– Memory management unit
MPU
– Memory protection unit
PBRIDGE – Peripheral I/O bridge
S/B
– Stand-by
SIU
– System integration unit
SPE2
– Signal processing engine 2
SPI
– Serial peripheral interface controller
SRAM – General-purpose static RAM
UART/LIN – Universal asynchronous receiver/transmitter/
local interconnect network
VLE
– Variable length instruction encoding
Figure 1. Block diagram
PXR40 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
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