PXR40 Datasheet, PDF (73/100 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

5.11 AC specifications
Electrical characteristics
5.11.1 Clocking
Figure 8 shows the operating frequency domains of various blocks on PXR40.
PLLCFG[0:1]
CORE
EXTAL
PLL
SYSDIV ^fsys
2
X
IPG DIV SEL
SIU_SYSDIV[SYSCLKDIV[0:1]]
X = 2, 4, 8, or 16
SIU_SYSDIV[BYPASS]
X=1
ETPU DIV SEL
SIU_SYSDIV[IPCLKDIV[0:1]]
SIU_ECCR[EBDF[0:1]]
Note: t_cycsys = 1 / f_sys
t_cyc = 1 / f_platf
2 = divide-by-2
 X = divide-by-X, depending on SIU_SYSDIV[BYPASS]
and SIU_SYSDIV[SYSCLKDIV].
f_platf
f_periph
f_etpu
PLATFORM /
BLOCKS /
FLASH
eTPU /
NDEDI
f_{ebi_cal}
DIV
EBI
CAL BUS
D_CLKOUT
(D_CLKOUT is not available
on all packages and cannot
be programmed for faster
than fsys/2.)
Figure 8. PXR40 block operating frequency domain diagram
Table 25 shows the operating frequencies of various blocks depending on the device’s clocking mode configuration settings (see
Table 26 and Table 27 for descriptions of bit settings).
Table 25. PXR40 operating frequencies^{1, 2}
Mode
SIU_ECCR
[EBDF[0:1]]³
f_sys
(core)
Enhanced
01
264
11
264
Full
01
200
11
200
Legacy
01
132
11
132
1 _{The values in the table are specified at:}
V_DD = 1.02 V to 1.32 V
V_DDE = 3.0 V to 3.6 V
V_DDEH = 4.5 V to 5.5 V
V_DD33 and V_DDSYN = 3.0 V to 3.6 V
T_A = T_L to T_H.
f_platf
f_etpu
(platform and all blocks (eTPU, eTPU RAM,
except eTPU)
and NDEDI)
132
132
132
132
100
200
100
200
132
132
132
132
f_{ebi_cal}^4,5
66
33
50
25
66
33
Unit
MHz
MHz
MHz
PXR40 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
73