PXR40 Datasheet, PDF (59/100 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Electrical characteristics
Table 8. PMC electrical specifications (continued)
ID
Name
Parameter
Min
Typ
Max
Unit
14d V_LVDASTEP Trimming step LVD VDDA
—
20
—
mV
15 —
SMPS regulator output resistance
—
15
25
Ohm
Note: Pullup to VDDREG when high, pulldown
to VSSREG when low.
16 —
17 —
SMPS regulator clock frequency (after reset)
1.0
1.5
2.4
MHz
SMPS regulator overshoot at start-up²
—
1.32
1.4
V
18 —
SMPS maximum output current
—
1.0
—
A
19 —
Voltage variation on current step² (20% to 80%
—
of maximum current with 4 µsec constant time)
—
0.1
V
1 _{VRC linear regulator is capable of sourcing a current up to 20 mA and sinking a current up to 500 µA. When using the}
recommended ballast transistor the maximum output current provided by the voltage regulator VRC/ballast to the VDD core
voltage is up to 1A.
2 _{Parameter cannot be tested; this value is based on simulation and characterization.}
5.6 Power up/down sequencing
There is no power sequencing required among power sources during power up and power down in order to operate within
specification as long as the following two rules are met:
• When VDDREG is tied to a nominal 3.3V supply, VDD33 and VDDSYN must be both shorted to VDDREG.
• When VDDREG is tied to a 5V supply, VDD33 and VDDSYN must be tied together and shall be powered by the
internal 3.3V regulator.
The recommended power supply behavior is as follows: Use 25 V/millisecond or slower rise time for all supplies. Power up
each V_DDE/V_DDEH first and then power up V_DD. For power down, drop V_DD to 0 V first, and then drop all V_DDE/V_DDEH
supplies. There is no limit on the fall time for the power supplies.
Although there are no power up/down sequencing requirements to prevent issues like latch-up, excessive current spikes, etc.,
the state of the I/O pins during power up/down varies according to Table 9 and Table 10.
Table 9. Power sequence pin states for MH and AE pads
VDD VDD33 VDDE
MH Pad
MH+LVDS Pads¹
AE/up-down Pads
High
—
High
Low
High
High
Normal operation
Pin is tri-stated (output buffer,
input buffer, and weak pulls
disabled)
Normal operation
Outputs driven high
Normal operation
Pull-ups enabled,
pull-downs disabled
Low
High
Low
Output low,
pin unpowered
Low
High
High Pin is tri-stated (output buffer,
input buffer, and weak pulls
disabled)
1 _{MH+LVDS pads are output-only.}
Outputs disabled
Outputs disabled
Output low,
pin unpowered
Pull-ups enabled,
pull-downs disabled
PXR40 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
59