PXR40 Datasheet, PDF (46/100 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Table 2. Signal Properties and Muxing Summary (continued)
Signal Name²
Function⁴
213 WKPCFG_NMI_
GPIO213
208 PLLCFG0_IRQ4_
GPIO208
209 PLLCFG1_IRQ5_
GPIO209
— PLLCFG2
— XTAL
— EXTAL
214 ENGCLK
P WKPCFG
A1 NMI
A2 —
G GPIO213
P PLLCFG0
A1 IRQ4
A2 —
G GPIO208
P PLLCFG1
A1 IRQ5
A2 SOUTD
G GPIO209
P PLLCFG2
P XTAL
P EXTAL
P ENGCLK
— EVTI
–¹³ EVTI
227 EVTO
–¹³ EVTO
(the BAM uses this pin to
select if auto baud rate is on
or off)
219 MCKO
–¹³ MCKO
Function Summary
State
during
RESET⁷
State
after
RESET⁸
Package
Location
(416)
Weak pull configuration input
Critical interrupt to core¹¹
—
GPIO
FMPLL mode configuration input
External interrupt request
—
GPIO
FMPLL mode configuration input
External interrupt request
DSPI D data output
GPIO
FMPLL mode configuration input
I MH
I
—
I
I MH
I
—
I/O
I MH
I
O
I/O
I MH
Crystal oscillator output
O AE
Crystal oscillator input
I
AE
EBI engineering clock output
O
F
Note: EXTCLK (External clock input)
selected through SIU register)
JTAG and Nexus
(see footnote¹² about resets)
Nexus event in
Nexus event out
I
F
O
F
V_DDEH1 WKPCFG/Up
Input/Up
V_DDEH1 PLLCFG/Up
Input/Up
V_DDEH1 PLLCFG/Up
Input/Up
(for Rev2 of
the device:
—/Up)
V_DDEH1
V_DD33
V_DD33
V_DDE2
PLLCFG/
Down
XTAL
EXTAL
ENGCLK/
Enabled
PLLCFG/
Down
XTAL
EXTAL
ENGCLK/
Enabled
V_DDE2
V_DDE2
—/Up
ABS/Up
EVTI/Up
EVTO/HI
N3
R3
P2
P3
AC26
AB26
AD1
T4
U1
Nexus message clock out
O
F
V_DDE2
O/Low
Disabled¹⁴
T2