PXR40 Datasheet, PDF (68/100 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Electrical characteristics
5.9 eQADC electrical characteristics
Table 17. eQADC Conversion Specifications (Operating)
Spec
Characteristic
Symbol
Min
Max
Unit
1 ADC Clock (ADCLK) Frequency
f_ADCLK
2
16
MHz
2 Conversion Cycles
CC
Single Ended Conversion Cycles 12 bit resolution
Single Ended Conversion Cycles 10 bit resolution
Single Ended Conversion Cycles 8 bit resolution
Note: Differential conversion (min) is one clock
cycle less than the single-ended
conversion values listed here.
2 + 14
2 + 12
2 + 10
128 + 14
128 + 12
128 + 10
ADCLK cycles
3 Stop Mode Recovery Time¹
4 Resolution²
T_SR
10
—
s
—
1.25
—
mV
5 INL: 8 MHz ADC Clock³
INL8
–4⁴
4⁴
LSB⁵
6 INL: 16 MHz ADC Clock³
INL16
–8⁴
8⁴
LSB
7 DNL: 8 MHz ADC Clock³
DNL8
–3⁴
3⁴
LSB
8 DNL: 16 MHz ADC Clock³
DNL16
–3⁴
3⁴
LSB
9 Offset Error without Calibration
OFFNC
0⁴
100⁴
LSB
10 Offset Error with Calibration
OFFWC
–4⁴
4⁴
LSB
11 Full Scale Gain Error without Calibration
GAINNC
–120⁴
0⁴
LSB
12 Full Scale Gain Error with Calibration
GAINWC
–4^4,6
4^4,6
LSB
13 Non-Disruptive Input Injection Current ^{7, 8, 9, 10}
14 Incremental Error due to injection current^{11, 12}
15 TUE value at 8 MHz ^{13, 14} (with calibration)
I_INJ
E_INJ
TUE8
–3
–4⁴
–4^4,6
3
m
4⁴
Counts
4^4,6
Counts
16 TUE value at 16 MHz ^{13, 14} (with calibration)
TUE16
–8
8
Counts
17 Maximum differential voltage¹⁵
(DANx+ - DANx-) or (DANx- - DANx+)
PREGAIN set to 1X setting
PREGAIN set to 2X setting
PREGAIN set to 4X setting
DIFF_max
—
(V_RH – V_RL)/2
V
DIFF_max2
—
(V_RH – V_RL)/4
V
DIFF_max4
—
(V_RH - V_RL)/8
V
18 Differential input Common mode voltage¹⁵
DIFF_cmv (V_RH – V_RL)/2 (V_RH – V_RL)/2
V
(DANx- + DANx+)/2
– 5%
+ 5%
1 _{Stop mode recovery time is the time from the setting of either of the enable bits in the ADC Control Register to the time that}
the ADC is ready to perform conversions. Delay from power up to full accuracy = 8 ms.
2 _{At VRH – VRL = 5.12 V, one count = 1.25 mV without using pregain.}
3 _{INL and DNL are tested from VRL + 50 LSB to VRH – 50 LSB. The eQADC is guaranteed to be monotonic at 10 bit accuracy}
(12 bit resolution selected).
4 _{New design target. Actual specification will change following characterization. Margin for manufacturing has not been fully}
included.
5 _{At VRH – VRL = 5.12 V, one LSB = 1.25 mV.}
6 _{The value is valid at 8 MHz, it is ±8 counts at 16 Mhz.}
7 _{Below disruptive current conditions, the channel being stressed has conversion values of $3FF for analog inputs greater than}
V_RH and $000 for values less than V_RL. Other channels are not affected by non-disruptive conditions.
PXR40 Microcontroller Data Sheet, Rev. 1
68
Freescale Semiconductor