PXR40 Datasheet, PDF (74/100 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Electrical characteristics
2 _{Up to the maximum frequency rating of the device (refer to Table 39). The fsys speed is the nominal maximum frequency.}
270 Mhz parts allow for 264 Mhz system clock + 2% FM.
3 _{See the PXR40 Reference Manual for full description as not all bit combinations are valid.}
4 _{EBI/Calibration bus is not available in all packages.}
5 _{The EBI/Calibration Bus operating frequency, febi_cal , depends on clock divider settings of block’s max allowed}
frequency of operation. Normally f_{ebi_cal} = f_platf /2, but can be limited to < f_platf /2 in Full Mode.
SIU_SYSDIV
[IPCLKDIV[0:1]]
00
01
10
11
Table 26. IPCLKDIV settings
Mode
Description
Enhanced
Full
—
Legacy
CPU frequency is doubled (Max 264Mhz). Platform,
peripheral, and eTPU clocks are 1/2 of CPU frequency
CPU and eTPU frequency is doubled (Max 200Mhz).
Platform and peripheral clocks are 1/2 of CPU frequency.
Reserved
CPU, eTPU, platform, and peripheral’s clocks all run at
same speed (Max 132Mhz).
Table 27. SYSCLKDIV settings
SIU_SYSDIV
[SYSCLKDIV[0:1]]
Description
00
Divide by 2.
01
Divide by 4.
10
Divide by 8.
11
Divide by 16.
5.11.2
Spec
1
2
3
4
5
6
Pad AC specifications
Table 28. Pad AC specifications (v_ddeh = 5.0 V, V_DDE = 3.3 V)¹
Pad
SRC/DSC
Out Delay^2,4
L  H/H  L (ns)
Rise/Fall^3,4
(ns)
Medium⁵
00
152/165
70/74
205/220
96/96
01
28/34
12/15
52/59
28/31
11
12/12
5.3/5.9
32/32
22/22
Load Drive
(pF)
50
200
50
200
50
200
PXR40 Microcontroller Data Sheet, Rev. 1
74
Freescale Semiconductor