PXR40 Datasheet, PDF (50/100 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Table 2. Signal Properties and Muxing Summary (continued)
Signal Name²
Function⁴
Function Summary
State
during
RESET⁷
State
after
RESET⁸
Package
Location
(416)
— TEST
— TEST
Test mode select (not for customer
I
F
V_DDEH1 TEST/Down TEST/Down
B4
use)
— VDDSYN
— VSSSYN
— VSTBY
— REGSEL
— VDDSYN
— VSSSYN
— VSTBY
— REGSEL
Clock synthesizer power input
Clock synthesizer ground input
SRAM standby power input
Selects regulator mode
(Linear/Switch mode)
I VDDE V_DDSYN
I VSSE V_DDSYN
I
VHV V_DDEH1
I
AE
V_DDREG
VDDSYN
VSSSYN
VSTBY
REGSEL
VDDSYN
VSSSYN
VSTBY
REGSEL
AD26
AA26
M4
W23
— REGCTL
— REGCTL
Regulator controller output to
base/gate of power transistor
O
AE
V_DDREG
REGCTL
REGCTL
Y26
— VSSFL
— VSSFL
Tie to V_SS
I
VSS V_DDREG
VSSFL
VSSFL
AB25
— VDDREG
— VDDREG
Source voltage for on-chip regulators
and Low voltage detect circuits
I VDDINT V_DDREG
VDDREG
VDDREG
AA25
1 _{The GPIO number is the same as the corresponding pad configuration register (SIU_PCRn) number in pins that have GPIO functionality. For pins that do not}
have GPIO functionality, this number is the PCR number.
2 _{The primary signal name is used as the pin label on the BGA map for identification purposes. However, the primary signal function is not available on all devices}
and is indicated by a dash in the following table columns: Signal Functions, P/F/G, and I/O Type.
3 _{P/A/G stands for Primary/Alternate/GPIO. This column indicates which function on a pin is Primary, Alternate 1, Alternate 2, (Alternate n) and GPIO.}
4 _{Each line in the Function column corresponds to a separate signal function on the pin. For all device I/O pins, the primary, alternate, or GPIO signal functions}
are designated in the PA field of the SIU_PCRn registers except where explicitly noted.
5 _{MH = High voltage, medium speed}
F = Fast speed
FS = Fast speed with slew
AE = Analog with ESD protection circuitry (up/down = pull up and pull down circuits included in the pad)
VHV = Very high voltage
6 _{VDDE (fast I/O) and VDDEH (slow I/O) power supply inputs are grouped into segments. Each segment of VDDEH pins can connect to a separate 3.3–5.0 V}
(+5%/–10%) power supply input. Each segment of VDDE pins can connect to a separate 1.8–3.3 V (±10%) power supply.
7 _{The Status During Reset pin is sampled after the internal POR is negated. Prior to exiting POR, the signal has a high impedance. The terminology used in}
this column is: O – output, I – input, Up – weak pull up enabled, Down – weak pulldown enabled, Low – output driven low, High – output driven high, ABS —
Auto Baud Select (during Reset or until JCOMP assertion). A dash on the left side of the slash denotes that both the input and output buffers for the pin are
off. A dash on the right side of the slash denotes that there is no weak pull up/down enabled on the pin. The signal name to the left or right of the slash indicates
the pin is enabled.
8 _{The Function After Reset of a GPI function is general purpose input. A dash on the left side of the slash denotes that both the input and output buffers for the}
pin are off. A dash on the right side of the slash denotes that there is no weak pull up/down enabled on the pin.