PXR40 Datasheet, PDF (60/100 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Electrical characteristics
Table 10. Power sequence pin states for F and FS pads
VDD VDD33 VDDE
F and FS pads
low
low
high
Outputs drive high
low
high
—
Outputs Disabled
high
low
low
Outputs Disabled
high
low
high
Outputs drive high
high
high
low Normal operation - except no drive current
and input buffer output is unknown.¹
high
high
high
Normal Operation
1 _{The pad pre-drive circuitry will function normally but since VDDE is unpowered}
the outputs will not drive high even though the output pmos can be enabled.
5.6.1 Power-up
If V_DDE/V_DDEH is powered up first, then a threshold detector tristates all drivers connected to V_DDE/V_DDEH. There is no limit
to how long after V_DDE/V_DDEH powers up before V_DD must power up. If there are multiple V_DDE/V_DDEH supplies, they can
be powered up in any order. For each V_DDE/V_DDEH supply not powered up, the drivers in that V_DDE/V_DDEH segment exhibit
the characteristics described in the next paragraph.
If V_DD is powered up first, then all pads are loaded through the drain diodes to V_DDE/V_DDEH. This presents a heavy load that
pulls the pad down to a diode above V_SS. Current injected by external devices connected to the pads must meet the current
injection specification. There is no limit to how long after V_DD powers up before V_DDE/V_DDEH must power up.
The rise times on the power supplies are to be no faster than 25 V/millisecond.
5.6.2 Power-down
If V_DD is powered down first, then all drivers are tristated. There is no limit to how long after V_DD powers down before
V_DDE/V_DDEH must power down.
If V_DDE/V_DDEH is powered down first, then all pads are loaded through the drain diodes to V_DDE/V_DDEH. This presents a heavy
load that pulls the pad down to a diode above V_SS. Current injected by external devices connected to the pads must meet the
current injection specification. There is no limit to how long after V_DDE/V_DDEH powers down before V_DD must power down.
There are no limits on the fall times for the power supplies.
5.6.3 Power sequencing and POR dependent on V_DDA
During power up or down, V_DDA can lag other supplies (of magnitude greater than V_DDEH/2) within 1 V to prevent any
forward-biasing of device diodes that causes leakage current and/or POR. If the voltage difference between V_DDA and V_DDEH
is more than 1 V, the following will result:
• Triggers POR (ADC monitors on V_DDEH1 segment which powers the RESET pin) if the leakage current path created,
when V_DDA is sufficiently low, causes sufficient voltage drop on V_DDEH1 node monitored crosses low-voltage detect
level.
• If V_DDA is between 0–2 V, powering all the other segments (especially V_DDEH1) will not be sufficient to get the part
out of reset.
• Each V_DDEH will have a leakage current to V_DDA of a magnitude of ((V_DDEH – V_DDA – 1 V(diode drop)/200 KOhms)
up to (V_DDEH/2 = V_DDA + 1 V).
PXR40 Microcontroller Data Sheet, Rev. 1
60
Freescale Semiconductor