PXR40 Datasheet, PDF (67/100 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Electrical characteristics
6 _{This specification applies to the period required for the PLL to re-lock after changing the MFD frequency control bits in the}
synthesizer control register (SYNCR). From power up with crystal oscillator reference, lock time will be additive with crystal
startup time.
7 _{For Flexray operation, duty cycle requirements are higher.}
8 _{Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fsys.}
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise
injected into the PLL circuitry via V_DDSYN and V_SSSYN and variation in crystal oscillator frequency increase the Cjitter
percentage for a given interval. D_CLKOUT divider set to divide-by-2.
9 _{Values are with frequency modulation disabled. If frequency modulation is enabled, jitter is the sum of Cjitter + Cmod.}
10 _{Modulation depth selected must not result in fpll value greater than the fpll maximum specified value.}
11 _{Maximum and minimum variation from programmed modulation depth is pending characterization. Depth settings available in}
control register are: 2%, 3%, and 4% peak-to-peak.
12 _{Depth tolerance is the programmed modulation depth ±0.25% of Fsys. Violating the VCO min/max range may prevent the}
system from exiting reset.
13 _{Modulation rates less than 400 kHz will result in exceedingly long FM calibration durations. Modulation rates greater than 1 MHz}
will result in reduced calibration accuracy.
14 _{Violating this range will cause the VCO max/min range to be violated with the default MFD settings out of reset.}
Table 16. Oscillator electrical specifications¹
(V_DDSYN = 3.0 V to 3.6 V, V_SS = V_SSSYN = 0 V, T_A = T_L to T_H)
Spec
Characteristic
1 Crystal Mode Differential Amplitude²
(Min differential voltage between EXTAL and XTAL)
Symbol
Min
V_{crystal_diff_amp} | V_extal – V_xtal | > 0.4 V
Max
—
Unit
V
2 Crystal Mode: Internal Differential Amplifier Noise
Rejection
V_{crystal_diff_amp_nr}
—
| V_extal – V_xtal | < 0.2 V V
3 EXTAL Input High Voltage
Bypass mode, External Reference
V_IHEXT
((V_DD33/2) + 0.4 V)
—
V
4 EXTAL Input Low Voltage
Bypass mode, External Reference
V_ILEXT
—
(V_DD33/2) – 0.4 V
V
5 XTAL Current³
I_XTAL
1
3
mA
6 Total On-chip stray capacitance on XTAL
C_{S_XTAL}
—
1.5
pF
7 Total On-chip stray capacitance on EXTAL
C_{S_EXTAL}
—
1.5
pF
8 Crystal manufacturer’s recommended capacitive load
C_L
See crystal spec See crystal spec pF
9 Discrete load capacitance to be connected to EXTAL
C_{L_EXTAL}
—
(2 × C_L – C_{S_EXTAL} pF
– C_{PCB_EXTAL4)}
10 Discrete load capacitance to be connected to XTAL
C_{L_XTAL}
—
(2 × C_L – C_{S_XTAL} pF
– C_{PCB_XTAL4)}
1 _{All values given are initial design targets and subject to change.}
2 _{This parameter is meant for those who do not use quartz crystals or resonators, but instead use CAN oscillators in crystal mode.}
In that case, V_extal – V_xtal  400 mV criterion has to be met for oscillator’s comparator to produce output clock.
3 _{Ixtal is the oscillator bias current out of the XTAL pin with both EXTAL and XTAL pins grounded.}
4 _{CPCB_EXTAL and CPCB_XTAL are the measured PCB stray capacitances on EXTAL and XTAL, respectively.}
PXR40 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
67