MC68HC05X4 Datasheet, PDF (91/156 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
Motorola CAN
Interface to the MC68HC05X4 CPU
Calculation of the bit time
BIT_TIME = SYNC_SEG + TSEG1 + TSEG2
NOTE:
TSEG2 must be at least 2 t_SCL, i.e. the configuration bits must not be
000. (If three samples per bit mode is selected then TSEG2 must be at
least 3 t_SCL.)
TSEG1 must be at least as long as TSEG2.
The synchronization jump width (SJW) may not exceed TSEG2, and
must be at least t_SCL shorter than TSEG1 to allow for physical
propagation delays.
i.e. in terms of t_SCL:
SYNC_SEG = 1
TSEG1 ≥ SJW + 1
TSEG1 ≥ TSEG2
TSEG2 ≥ SJW
and
TSEG2 ≥ 2
(SAMP = 0)
or
TSEG2 ≥ 3
(SAMP = 1)
These boundary conditions result in minimum bit times of 5 t_SCL, for one
sample, and 7 t_SCL, for three samples per bit.
23-mcan
Motorola CAN
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MC68HC05X4 Rev 1.0