MC68HC05X4 Datasheet, PDF (41/156 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
CPU
Instruction Set Summary
Table 6. Instruction Set Summary (Continued)
Source
Form
Operation
BHS rel
BIH rel
BIL rel
BIT #opr
BIT opr
BIT opr
BIT opr,X
BIT opr,X
BIT ,X
BLO rel
BLS rel
BMC rel
BMI rel
BMS rel
BNE rel
BPL rel
BRA rel
Branch if Higher or Same
Branch if IRQ Pin High
Branch if IRQ Pin Low
Bit Test Accumulator with Memory Byte
Branch if Lower (Same as BCS)
Branch if Lower or Same
Branch if Interrupt Mask Clear
Branch if Minus
Branch if Interrupt Mask Set
Branch if Not Equal
Branch if Plus
Branch Always
BRCLR n opr rel Branch if Bit n Clear
BRN rel
Branch Never
BRSET n opr rel Branch if Bit n Set
BSET n opr
Set Bit n
BSR rel
CLC
Branch to Subroutine
Clear Carry Bit
Description
Effect on
CCR
H I NZC
PC ← (PC) + 2 + rel ? C = 0 — — — — — REL 24 rr 3
PC ← (PC) + 2 + rel ? IRQ = 1 — — — — — REL 2F rr 3
PC ← (PC) + 2 + rel ? IRQ = 0 — — — — — REL 2E rr 3
(A) ∧ (M)
IMM A5 ii 2
DIR B5 dd 3
— — ¤◊ ¤ —
EXT
IX2
C5 hh ll 4
D5 ee ff 5
IX1 E5 ff 4
IX F5
3
PC ← (PC) + 2 + rel ? C = 1 — — — — — REL 25 rr 3
PC ← (PC) + 2 + rel ? C ∨ Z = 1 — — — — — REL 23 rr 3
PC ← (PC) + 2 + rel ? I = 0 — — — — — REL 2C rr 3
PC ← (PC) + 2 + rel ? N = 1 — — — — — REL 2B rr 3
PC ← (PC) + 2 + rel ? I = 1 — — — — — REL 2D rr 3
PC ← (PC) + 2 + rel ? Z = 0 — — — — — REL 26 rr 3
PC ← (PC) + 2 + rel ? N = 0 — — — — — REL 2A rr 3
PC ← (PC) + 2 + rel ? 1 = 1 — — — — — REL 20 rr 3
PC ← (PC) + 2 + rel ? Mn = 0
DIR (b0) 01 dd rr 5
DIR (b1) 03 dd rr 5
DIR (b2) 05 dd rr 5
—
—
—
—
¤◊
DIR (b3)
DIR (b4)
07
09
dd rr
dd rr
5
5
DIR (b5) 0B dd rr 5
DIR (b6) 0D dd rr 5
DIR (b7) 0F dd rr 5
PC ← (PC) + 2 + rel ? 1 = 0 — — — — — REL 21 rr 3
PC ← (PC) + 2 + rel ? Mn = 1
DIR (b0) 00 dd rr 5
DIR (b1) 02 dd rr 5
DIR (b2) 04 dd rr 5
—
—
—
—
◊¤
DIR (b3)
DIR (b4)
06
08
dd rr
dd rr
5
5
DIR (b5) 0A dd rr 5
DIR (b6) 0C dd rr 5
DIR (b7) 0E dd rr 5
Mn ← 1
DIR (b0) 10 dd 5
DIR (b1) 12 dd 5
DIR (b2) 14 dd 5
—
—
—
—
—
DIR (b3)
DIR (b4)
16
18
dd
dd
5
5
DIR (b5) 1A dd 5
DIR (b6) 1C dd 5
DIR (b7) 1E dd 5
PC ← (PC) + 2; push (PCL)
SP ← (SP) – 1; push (PCH)
SP ← (SP) – 1
PC ← (PC) + rel
— — — — — REL AD rr 6
C←0
— — — — 0 INH 98
2
15-cpu
CPU
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MC68HC05X4 Rev 1.0