MC68HC05X4 Datasheet, PDF (85/156 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
Motorola CAN
Interface to the MC68HC05X4 CPU
OIF — Overrun interrupt flag
When OIE is set then this bit will be set when a data overrun condition
is detected. Like all the bits in this register, OIF is cleared by reading
the register, or when reset request is set.
1 = A data overrun has been detected.
0 = No data overrun has occurred.
EIF — Error interrupt flag
When EIE is set then this bit will be set by a change in the error or bus
status bits in the MCAN status register. Like all the bits in this register,
EIF is cleared by reading the register, or by an external reset.
1 = There has been a change in the error or bus status bits in CSTAT.
0 = No error interrupt has occurred.
TIF — Transmit interrupt flag
The TIF bit is set at the end of a transmission whenever both the TBA
and TIE bits are set. Like all the bits in this register, TIF is cleared by
reading the register, or when reset request is set.
1 = Transmission complete, the transmit buffer is accessible.
0 = No transmit interrupt has occurred.
RIF — Receive interrupt flag
The RIF bit is set by the MCAN when a new message is available in
the receive buffer, and the RIE bit in CCNTRL is set. At the same time
RBS is set. Like all the bits in this register, RIF is cleared by reading
the register, or when reset request is set. After sending a message by
the MCAN module, the RIF bit will not be set, even though this
message has been written into the receive buffer following successful
transmission.
1 = A new message is available in the receive buffer.
0 = No receive interrupt has occurred.
17-mcan
Motorola CAN
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MC68HC05X4 Rev 1.0